The present disclosure herein relates to a semiconductor memory device, and more particularly, to a variable resistance memory device compensating a difference of a resistance of a bit line.
Semiconductor memory devices are devices that store data and read the stored data when necessary. Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices.
Volatile memory devices loose their stored data when their power supplies are interrupted. Volatile memory devices include SRAM, DRAM and SDRAM. Nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Nonvolatile memory devices include ROM, PROM, EPROM, EEPROM, a flash memory device, PRAM, MRAM and FRAM.
Example embodiments provide a variable resistance memory device. The variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit which is connected to the first and second memory cells through word lines and is configured to select the first and second memory cells. The select circuit is configured to compensates for a difference of resistances in the different lengths of the bit lines.
Example embodiments provide a memory device including a data input unit, a memory cell array and a row select circuit. The memory cell array includes at least a first memory cell and a second memory cell connected to the data input unit though a bit line. A portion of the bit line between the data input unit and the first memory cell has a first bit line resistance and a portion of the bit line between the data input unit and the second memory cell has a second bit line resistance. The row select circuit includes a first selection device connected to the first memory cell through a first word line and a second selection device connected to the second memory cell through a second word line. A portion of the first word line between the first selection device and the first memory has a first word line resistance and a portion of the second word line between the second selection device and the second memory has a second word line resistance. Resistances of the first selection device and the second selection device being configured based on at least the first and second bit line resistances.
According to example embodiments, the resistances of the first selection device and the second selection device are configured so that a sum of the resistance of the first selection device, the first word line resistance and the first bit line resistance equals a sum of the resistance of second selection device, the second word line resistance and the second bit line resistance.